1. Technical Field
This disclosure relates to semiconductor memories and more particularly, to an improved delay lock loop including feedback for synchronizing a system clock with data output lines.
2. Description of the Related Art
Semiconductor memories, such as synchronous dynamic random access memories (SDRAMs) and specific Double Data Rate (DDR) memories, typically include delay lock loops (DLLs). DLLs function to cancel on-chip amplification and buffering delays, and DLLs improve input/output timing margins. DDR SDRAMs are designed such that READ/WRITE data on output lines (DQ pins) are synchronized to a system clock, for example VCLK.
On-chip delay is conventionally "modeled" in a DLL feedback loop to match the delay of "real" circuit components such as, a receiver, a driver, an off chip driver (OCD) and packaging of the chip. Conventional memory chips employing the "modeled" delay often use an inverter chain or similar techniques to account for delays. The accuracy of the matched delay is an important parameter in phase alignment between an incoming clock signal, VCLK, and DQs. Conventional techniques such as those described stiffer from mismatches from the "real" circuit delay in terms of technology variation and temperature behavior. Further, conventional techniques poorly match the packaging delay components caused by bondwire, lead inductance and capacitance together with the module/board level interface (e.g., Stub Series Terminated Logic (SSTL)).
Referring to FIGS. 1 and 2, a conventional DLL scheme is shown. DQ/QS (data output pads for the chip) to system clock synchronization is shown in terms of block diagrams. A desired timing budget is illustrated in FIG. 3. The clock path is split between a chip level (FIG. 1) and a packaging and/or module/board level (FIG. 2) including the interface, for example, an SSTL interface. The clock delay path includes the following:
1. At the chip level (FIG. 1), the incoming differential clock (vclk, vbclk) at a pad on chip V.sub.-- PC is amplified through a receiver RCV to a refclk signal (REFCLK) and further delayed in a DLL (DLLCLK) and redriven at a driver DRV to control an off chip driver circuit (OCD) and DQ pad (DQ/QS) on a chip DQ-PC.
2. At the packaging and module/board (interface) level (FIG. 2), from chip pad DQ.sub.-- PC on, the delay path includes a bondwire (BW) and leadframe (lead) inductance delay, L.sub.BW+Lead, to a DQ-Pin of a module DQP with the interface SSTL including Rstub (stub resistance at the board level, which may be about 25 .OMEGA.) and Rterm (termination resistance on the board level), TL (transmission line impedance, which may Z.sub.o about 50 .OMEGA.) and CL for the capacitive load. VTT or V.sub.term is the termination voltage. If synchronized the system clock vclk/bclk is aligned with DQ/QS signal on pin DQP as shown at line A in the timing diagram of FIG. 3.
Referring to FIG. 4, a block diagram of a conventional DLL circuit with receiver RCV and off chip driver OCD mimic circuits in block 30. Other components include a delay line including delay line elements in block 32, a phase detector (PD), a delay control (DL control), a filter 33 and a modeled delay feedback loop 34. The input reference clock (REFCLK) drives the delay line 32 of the DLL and the output (DLLCLK) is feedback (feedback clock--FB.sub.-- CLK) through the RC-delay-mimic feedback circuit in block 30 to phase detector PD. The output of phase detector PD goes to the filter 33 which includes logic circuitry to provide an increase (inc) and decrease (dec) signals of the filter. The inc and dec signals of the filter control the delay line 32 and adjust the variable delay between REFCLK and DLLCLK so that REFCLK and FB.sub.-- CLK are synchronized/aligned.
The RC-delay-mimic circuits mimic the delay of receiver RCV, driver DRV, OCD, and package P (See FIGS. 1 and 2) delays. The RC-delay-mimic circuits usually include an inverter chain to match the delay of the "real" circuits. As described above, one of the disadvantages of this technique is that the inverter circuits do not totally match the "real" circuit delay in terms of technology variation and temperature behavior. In addition, the inverter circuits poorly match the packaging delay components caused by bondwire, lead inductance and capacitance together with the module/board level interface.
Therefore, a need exists for an improved delay lock loop with feedback that more accurately models delays. A further need exists for an improved delay lock loop which avoid deviations in delay due to technology and temperature effects.